"MAREBO" has been designed in the first TEMIC semiconductors Multi-Project-Wafer of the DMILL radhard BiCMOS technology. It contains 12 columns of 63 pixels. The size of the whole chip is 7.3mm *5.5mm and the size of the active area is 5.2mm*3.2mm. The layout of one pixel which includes an analog part (amplifier and discriminator), control logic (register and latches) and a read-out part. The total pixel area is 50u*397u but has been stretched to 50u*433.4u in order to fit with existing n+/n and diamond detectors. In term of level of integration, DMILL and AMS BiCMOS 0.8u technology can be easily compared by measuring the sizes of the "MAREBO" pixel cell and of the FE-A pixel cell. Since the control logic part takes 15-20% more room in DMILL with respect to the one in AMS, the sizes of both analog parts are the same (144um for DMILL and 141um for AMS). In fact, in DMILL, each transistor is isolated by insulating trenches but the "trench to trench" rule is twice less stringent than the "well to well" or "active to well" rules in a standard technology. Since, for analog designs, well-transistors have usually their dedicated substrate, the transfer in DMILL has no impact on the size. Concerning digital parts, wells are merged to avoid the "well to well" rule and, consequently, the design is shrinked in a range of 20%.
The main goal of the "MAREBO" chip was to reach LHC requirements in terms of electrical specifications and radiation tolerance.
The amplifier is a folded cascode charge sensitive amplifier. Its feedback capacitance is 3fF. It is buffered by a nMOS type follower. These two full-CMOS stages are fed back by a enhanced version of the circuit used in the "Beer & Pastis" chip. This improved DC feedback scheme has already been implemented in the MBTS1 chip (Marseille Bonn Test Structure 1) submitted in the AMS BiCMOS 0.8u technology and after put on the FE-A chip. Special attention has been paid to simulate the cell with worst case models which include process variation and shift of main parameters after high levels of irradiation.
Fig. XXX1. depicts the non-averaged responses of the charge sensitive amplifier at input charges of 5000, 10000, 15000, 20000 and 25000 electrons. The x-scale is 200 ns per division and the y-scale is 200 mV per division. All measurements have been carried out with a power consumption of 40 uW per pixel. The slope of the recovery period remains constant at different input charges and after calculation, the value of the feedback capacitance is close to the one expected in simulation. Fig. XXX2. shows the behavior of the charge sensitive amplifier at different feedback currents. These currents were set at 1 nA, 2 nA, 3 nA, 4 nA and 8 nA while the input charge was kept constant at 10000 electrons. The main goal of these curves is to demonstrate that the amplifier remains stable even for shaping times in the range of the rise time. Clearly, the ballistic deficit is negligible. For this figure, the x-scale is 200 ns per division and the y-scale is 100 mV per division. In order to extract the intrinsic pixel noise, the efficiency versus input charge of the complete cell has been measured. For a threshold close to 2500 electrons, the calculation of the pixel noise gives a value of 80 electrons without detector and 250 electrons when the amplifier is connected to a diode. One of the most critical points in reaching the LHC specification is that of leakage current tolerance. Fig. XXX3. shows that the variation in pixel threshold remains in a range of a few hundred electrons even for leakage currents as high as 100 nA, close to that expected after 10 years of LHC operation. The behavior of the charge sensitive amplifier at leakage currents of 0 nA, 25 nA, 50 nA, 75 nA and 100 nA shows that the shaping time is slightly decreased but tends to saturate after 50 nA. This effect is clearly demonstrated when very high leakage currents are injected, and tests show that the threshold is only slightly increased even after values greater than 200 nA. 
The discriminator is AC coupled to the amplifier. The input stage of this comparator has been implemented with a differentiel pair of bipolar transistors for speed and matching purposes. The width of the discriminator output shape can be used for analog charge information according to the Time Over Threshold technique, demonstrating that a 4-5 bits amplitude resolution is easily achievable. Fig. XXX4. depicts the time walk of the pixel cell versus the charge above the threshold of 2200 electrons for an amplifier without input capacitance, 2200 electrons for an amplifier whose input has been connected to a 200fF parasitic capacitance and 2900 electrons for an amplifier connected to a diode. Tests show that time walk decreases at higher thresholds. The measurement has been carried out in a range from 100 electrons above threshold to 100000 electrons. Special attention has been paid to reduce the minimum charge above threshold that can be tagged within a window of 25 ns relatively to a very large signal. This is demonstrated in Fig. XXX4. (left curve) where a saturation appears at the charge corresponding to a MIP in 300 um silicon and where the curve is even reversed at higher charges. The idea was to force the input bipolar transistor going into its linear region and, consequently, slow down the discriminator for input charges above the MIP by saturating it. This technique allows the minimum charge to be reduced to 500-600 electrons above the threshold (Fig. XXX4. right curve) for a pixel cell with an input capacitance of 200 fF or connected to a n+/n detector.
Clearly, the cell-to-cell threshold mismatch is a crucial point for realizing an accurate pixel detector. In particular, it determines the minimum threshold that can be set. A low dispersion will permit the array threshold to be decreased without causing oscillating pixels. The upper part of the threshold spread limits the minimum threshold that can be set. Even good dispersion results are obtained without independent pixel adjust on the previous Beer&Pastis chip (sigma = 90 electrons) and on the MAREBO chip (see below), a 3-bit DAC has been implemented in each cell in order to eliminate tails in the dispersion distribution and to keep control on the threshold variation. This will be helpful when, after high level of irradiation, only half charge will be collected in the partially depleted detector (at this point, the minimum threshold must be even low) and random parameter shifts of detector and electronics may occur. This fine-tuned threshold is based on a network of 8 switched pMOS resistors locally controlling the comparator bias system. The 3 bits are statically stored via the shift register in the control logic part. Comparing to the "Beer & Pastis" chip, Vcomp is now controlled by a voltage drop generated by a constant current source (Itr) in switched resistors. Consequently, the signals which tune the threshold are:
-Vth which performs the coarse tune of the whole array.
-Itr which tunes the steps of the fine tune (linear with 1uA for 100 electrons step).
-3 bits per pixel for the fine tune.
Fig. XXX5. (right part) shows that the differentiel linearity error of the 3-bit DAC is 14% which is better than needed for this application. With Itr set to 1uA, the threshold is decreased by around 100 electrons per DAC step which is consistent with simulation. The left part of Fig. XXX5. shows the efficiency curves of one pixel at each step of the DAC. This demonstrates that there is no extra noise induced by the setting of the adjustment.
Clearly, the linearity of the DAC versus Itr is a crucial point for realizing an accurate tuning. As demonstrated below, this linearity drastically eases the algorithm that calculates the value of each DAC for optimal threshold tune (optimal Itr is also fitted according the result without DAC action and the result with full range DAC action when itr is manually set to Itr0).
Fig. XXX6. depicts the 2 distributions before and after threshold tuning. The algorithm measures the distribution where all pixel DACs are set to 0 (right curve). With this set-up, the mean threshold is 1830 electrons and the standard deviation is 93 electrons. It automatically calculates the optimum Itr using DAC set to full range with an arbitrary Itr0 (it assumes that the behavior of Itr is linear). After recalculation of all DAC values, it performs a new array scan (left curve). As demonstrated, after adjustment, the mean threshold is lower (1462 electrons) and the standard deviation has been drastically reduced (40 electrons). Even if the spread before tuning is acceptable for LHC requirements, this correction could be of considerable interest after high level of irradiation.
Fig. XXX7. depicts the block diagram of the control section. Only one shift register is used to control either the injection, the mask or the 3 bits of the DACs. These shift registers are serially chained from pixel to pixel. The SERIN signal is connected to the pixel 63 of column 1 (pixel number 1 to 63 from bottom to top and column 1 to 12 from left to right) and the output of pixel 1 column 12 (last pixel of the chain) is buffered and can be monitored to be sure that the shift registers work properly. As there are 12*63 pixels; any information entered in the SERIN pad is output on the SEROUT pad after 756 rising edges of the SHIFTCLOCK. The register is basically a dynamic Flip-Flop which is converted to a static Flip-Flop when its clock is held at high level. The output of each register is directly connected to the pass-transistor used for enabling the injection. In parallel, shift register data is used to mask dead or noisy pixels. The procedure for masking one pixel is to address the pixel and then inject on the LOADMASK signal a rising edge which will statically latch the register information. Special attention has been paid to ease testing operation, in particular for the threshold scan of the matrix using the FAST-OR (HITBUS) and for the check of the read-out part during probe station testing.
Bit1, bit2 and bit3 of the DAC can be statically set by performing the same action as the masking action, but by sending a rising edge on LOADBIT1, LOADBIT2 and LOADBIT3 respectively.
The read-out part is basically the same used in the DMILL Lepton chip excepted that the input gate has been changed to allow Time Over Threshold tagging. There is no End-of-Column in this chip. Data coming at the bottom of the chip are latched, buffered and output. There is one clock pad per pair column. In total, there are 72 outputs (6 bits * 12 columns) and 6 clock pads.
In order to test the detector after flip-chip, the amplifier output of the cell 63 column 12 has an individual test output signal. For this purpose, a special two stage analog buffer has been studied. No input bias is needed, but if more current is required in the bipolar output stage, the power supply can be increased in the range of 3V-5V. The discriminator output has also been buffered and brought out to the OUTDISC pad.
An extra 4 pixel column has been added to allow more measurements. In particular, a current mirror has been implemented at the input of 2 pixels to test the output of the amplifier at different leakage currents for the first one and to measure the threshold shift after the discriminator of the second one. For this pixel, the 3 bits can be externally set.
Two direct input amplifiers have also been implemented to be wire bonded on n+/n diodes. This will allow to continue the work begun on p+/n detectors and to compare behaviour of both kinds of detectors.
This chip has been bumped to a n+/n detector and tested in beam in parallel with FE-A. A XILINX card specially dedicated to the MAREBO chip has been developed for test beam and irradiation test purposes. Very preliminary test beam results are shown in section??????????????????????. In the meantime, MAREBO is hybridized to a diamond detector and will be tested in beam in a very near future along with n+/n detectors. Irradiations will be carried out on both kind of detectors before putting them again in beam durind August 1998. This will allow us to investigate the behavior of real radhard packages electronics/detector (n+/n and diamond) after very high level of irradiation close to the one expected after 10 years of LHC operation.


Fig. XXX1. Response of the amplifier at different input charges
Fig. XXX2. Response of the amplifier at different feedback currents
Fig. XXX3. Threshold of the pixel cell versus leakage current
Fig. XXX4. Response of the pixel cell as a function of the injected charge above the threshold
Fig. XXX5. Threshold variation versus DAC value (with Itr=1 uA)
Fig. XXX6. Distribution of the matrix threshold before and after adjustment
Fig. XXX7. Schematic of the control logic part