-------- Original Message --------
Subject: ROD Hardware Modification
Date: Thu, 01 Apr 2004 17:36:45 -0800
From: John Joseph <JMJoseph@lbl.gov>
Organization: Lawrence Berkeley National Laboratory

 Hi John and John,

I found a problem on the RODs that I think requires immediate
attention.  The VME clock is a 5V CMOS signal and is connected to the
PRM FPGA which is not 5V tolerant.  The attached drawing shows the
modification required to reduce the amplitude of the clock signal into
the PRM.  The values that you use do not have to be the exact ones
shown, but they should be close.  The xtal oscillator can only source a
maximum of 16mA, and the mod as shown pulls 8mA when the output of the
oscillator is high.  I would like to keep the load in that range.  The
maximum high voltage should be less than 3.6V.  Sorry that I did not
catch this sooner, and I hope that all of the units in the field can be
modified at their respective institutes.

The RevC boards have the same problem, and should be updated when
possible.  (It's not as urgent, because these boards are closing in on
end of life status).

John H, the board you returned had a cracked solder joint on the FPGA
Flash.  The problem you saw is consistent with a flash failure, and I
was able to reproduce it here.  I repaired this today, and will send it
along with 3 more RevE boards to you tomorrow.

Please let me know if you have any questions.

Regards,
John