*) corresponding author. E-mail: "DELPIERRE@CPPM.IN2P3.FR"

1) Fachbereich Physik, universität Wuppertal, Postfach 100 127 D-42097, Wuppertal, Germany

2) Dipartimento di Fisica, Universita' degli Studi and INFN, Via Celoria 16, I-20133, Milano, Italy

3) LPC Collège de France, IN2P3-CNRS, 11 place M. Berthelot, F-75231 Paris Cedex 05, France

4) Centre de Physique des Particules de Marseille, IN2P3-CNRS, 123 av. de Luminy, BP907, F-13288 Marseille cedex 09, France

5) Institut für Experimentelle Kernphysik, Universität Karlsrhue, Postfach 6980, D-76128, Karlsrhue, Germany

6) Institut des Sciences Nucleaires, IN2P3-CNRS, Université de Grenoble 1, F-38020, Grenoble Cedex, France

7) CERN, CH1211, Geneva 23, Switzerland

8) Prague, Czeck Republic.

To improve tracking in the very forward direction for running at LEP200, the angular acceptance of the DELPHI Vertex detector has been extended from 45 degrees to 11 degrees with respect to the beam axis. Pixel detector crowns cover the region between 25 and 13 degrees. Due to very tight space and material thickness constraints it was necessary to develop new techniques (integrated busses in the detector substrate, high density layout on Kapton,...). About 1000 cm2 of pixels are already installed and working in DELPHI. Techniques, tests and production of these detectors will be described, as well as the main problems encountered during this work.

For new physics, running in LEP200, the DELPHI collaboration decided to extend the tracking acceptance in the very forward direction, from 45 degrees to 11 degrees (particle angle with respect to the beam) [1]. This was not only for the tracking, but also to improve the trajectory founding for the forward RICH counter. The length of the barrel strip layers was increased to reach 25 degrees, but to go to 11 degrees, it was necessary to add disks or crowns. These disks could be in strips or pixels. The pattern recognition studies demonstrated that a double layer of pixels, combined with two layers of X-Y strips would optimise the the cost versus tracking efficiency in these very forward region. Since intended for tracking rather than vertexing, the pixel size can be optimised to reduce the price (at this angle the vertexing is not possible because of the multiple scattering in the material). Though this project was very ambitious for many reasons (very restricted space, material and cooling constraints, large surface regarding the actual development of the technique, limited budget, ...) we accepted the challenge to increase the acceptance from 25 to 13 degrees with two layers of pixels (two layers of X-Y strips, which extend the acceptance to 11 degrees were also decided) (Fig. 1). The full first layer is now installed in DELPHI and the second layer is being completed and will be installed during the next LEP shut down.

We describe the design, the prototyping, prototype testing, the main problems and solutions, the fabrication processes and the mounting in the DELPHI detector.

The pixel detectors were built using a "hybrid technique"; a high resistivity silicon detector substrate with bump-bonded readout chips. However, because of very tight space and material limitations, readout busses were integrated in the detector substrate, by the use of a double metal process. Moreover, the drivers and control chips had to be far away (at least 25 cm), and we had to find a way to communicate signals to them with very thin cables. A priori it was not obvious that busses beside the depleted region of the detector would not modify the electric field and change the properties of the neighbouring pixels (this was never done before). The tests on prototypes proved that, with a guard ring in between, there is no loss in the detection efficiency. However, from these tests we found that the integrated busses are convenient for the data and the control lines, while their resistivity is too high for the power bussing. In addition, we need decoupling capacitors which are very difficult, even not possible, to integrate in the detector substrate. It was then necessary to add a Kapton ribbon layer over the chips with extra wire bonding. The final detector substrate is shown in Fig. 2. It includes 10 arrays of 24x24 pixels and six arrays of 16x24 pixels (that is about 8000 pixels of 330µm X 330µm per module).

The electronic chip includes an array of front end cells and a selective readout system which selects and reads only the hit pixels.

The initial design of the front end cell was developed in the RD19 collaboration [2]. It includes a charge amplifier, a comparator, a latch and switches. However, modifications were necessary to make it compatible with a larger input capacitance (larger contact pads, larger pixels) and with the selective readout system. Also, to be compatible with the DELPHI data acquisition system, a gate and fast reset were added [3].

The first prototypes gave us some bad surprises, not during tests of individual electronic chips, but after detector bonding. For example we had the so called "even-odd effect", where alternate column had different thresholds. We finally understood that this effect was due to the fact that the cells were assembled in the array in such a way that, from column to column the digital parts are together and not close to the analog part. Then a small misalignment of the bumps results on an increase of the input capacitance of the amplifier for one column but not for the other. We had also some trouble to avoid (reduce) bad effects of the dynamic behaviour of the current after the fast reset. After five iterations we had a chip which met DELPHI specifications.

The selective readout is based on the same idea as the SVX sparse data scan, but in two dimensions. That is when a pixel is hit it opens a line switch and a connection to a column switch (Fig. 3), in such a way that a readout signal at the top of the line bus, encodes the first line where there is a hit pixel then propagates to open the corresponding column switch. Then the column number is associated to the already encoded line number to give the pixel address. When, after reading all the pixels on this line, the signal arrives at the end of the column bus, it closes the switch in the line bus and the readout proceeds to the next line where there is a hit pixel. As implemented in the SACMOS/FASELEC 3 µm (from Philips) the readout time is less than 200 ns per hit pixel [4].

It is well known that, apart from the electronic chip, the main difficulty in pixels detectors is the bump-bonding. However, for this tracker, the pixels are large enough to have pads of 140 µm diameter, which is close to the standard size of the industrial technique named "tape-bonding", used for Kapton cable connections. We investigated two low cost techniques, "anisotropic conductive film" (at the IN2P3-CPPM, Marseille) and "screen printing" (at INFN-Milano). After 6 months of effort, we obtained, in both laboratories, a good success, that is less than one per thousand bad contacts. While that is satisfactory for a pixel detector array bonded to a single electronic chip for beam test, for a complete module of 16 chips we often had one or more chips not working. A very high contact efficiency is needed, not so much for the pixel array, but for the input/output pads. For 30 input/output pads per chip and 16 chips per module, a yield better than 90% requires less than 0.2 bad contact per thousand. Actually we were close to this level but, because of time, we decided to go to an industrial process. We chose one of the most reliable and less expensive processes, the IBM solder ball bonding [5]. To benefit from using an industrial process, we chose the finest technology (IBM-C4), and reduced the pad diameter to 100 µm to reduce the input capacitance. This was, from the beginning, a real success.

As described above, the data and control busses are integrated in the detector substrate and the power busses are on a superimposed Kapton ribbon. This ribbon serves also to support the decoupling capacitors which must be located close to the chips. It also serves to collect the data from both sides of the detector substrate in order to have only one data link to the external world. Since many busses are crossing on this ribbon, over a restricted surface, we had to use an advanced technique for the design and its fabrication. Bus signals are sent to the external world via multilayer printed circuit boards ("repeaters"), which include buffers, control circuits and power sharing busses and connectors. These were located 16 cm from the second layer of pixels and at 32 cm from the first layer. The link is done by double layer Kapton ribbon. The thickness of this Kapton is kept to a minimum (460 µm) and the shape is "smart" enough to pas through the very forward strip layers and also allow the Kapton from the barrel strips to reach their "repeaters".

From the detector substrate to the first Kapton and between the two Kaptons, the connections are done by wire bonding. This is not trivial since the Kapton is not a good support for wire bonding.

6.1. First tests of complete modules

The first tests of complete modules (with a radioactive source), gave bad results. The reason was that the chips had different bias, due to different bias input impedance. When the chips were sorted before bump bonding, the uniformity became very good (less than 5% variation). For production, we set up the on-wafer test described session 7.

6.2. Beam tests

The prototypes were tested in a CERN pion beam, with tracks defined in a telescope with four double planes of silicon strips with 50 µm of readout pitch (DELPHI strip detectors). This gives a track localisation of better than 3 µm at the surface of the pixel chip.

The efficiency was measured at a polar angle of 40 degrees, which corresponds to the average angle of the particles for the pixel modules installed in DELPHI. It was always around 100% for thresholds lower than 12000 electrons (Fig. 4).

At 90 degrees, the spatial resolution was 92 µm for single pixel clusters; expected from the pixel pitch of 330 µm. For clusters of two pixels the resolution was 12 µm, but for the small region (about 15µm where we can expect charge sharing). At 40 degrees, the spatial resolution is always better than 90 µm (Fig. 5) and it is optimum for a threshold of 7000 e- (better than 50 µm everywhere), which corresponds to half single and half double pixels per track. This confirms the advantage of using the charge sharing even in binary data readout. However, in DELPHI, we expect different effect which could degrade this very nice resolution (alignment error, effect of the Lorenz angle,...).

The different fabrication steps are the following :

1) Electronic chips :

2) Detector substrates (in parallel with the electronic chips):

3) Kaptons ribbons :

4) Module assembly :

Fabrication turn-around for detector substrates were 4 to 5 months, that for the electronic chips was 3 months and the total time for the other assembly operations was 2 months.

The test and sorting of the electronic chips was not a trivial operation. The holes in the passivation layer on the input/output pads, done for the bump-bonding, are too small to allow good contacts in a standard probe station. Chips were tested with specially designed probes, with flat edges, after bump deposition.

The test and sorting procedure is the following :

1) Rejection tests

The measurement of the detector leakage current onto the guard ring is simple but the test for short/open lines on the integrated busses is non-trivial. This is done by capacitance measurement on the wafers, with an automatic probe station modified for this purpose [6]. The method has been widely used by the same team for the test of strip detectors and works very well for any kind of conductive busses.

The yield at the different steps is as follows:

The processing yields (electronics, detectors and bump bonding) are very good, while the assembling yield was expected to be better. The loss of modules at the beginning were due to the following reasons :

The shorts between metal layers comes from some contact pads which are too close to the metal busses.

The data readout is by FASTBUS via local printed circuit "repeater" boards. The system was built by the College de France team.

The repeaters distribute the power voltage and sequence the control signals. They also contain the front end buffers and data drivers. Since local space is strictly restricted, connectors is one of the main problems. We use mini-connectors which are reliable if used carefully. The bias are the same for all the modules of one full crown (two repeaters), while the threshold current bias is individually adjustable by detector module.

The FASTBUS boards handles repeaters. There is one mother board (PIROM) and 4 daughter boards (PIROU), one per repeater. The timing signals come from the DELPHI timing distribution board (the PANDORA).

On the arrival of a first level trigger signal, the sparse data scan readout is started in all chips. At the second level trigger, the pixel addresses, stored in the chips, are read from chip to chip in serial mode by each PIROU.

The noisy pixels are filtered by the crate processor (the DELPHI FIP), based on the MOTOROLA 68030. It finds the pixels responding for more than 10% of the triggers and creates a mask for these pixels which is used as a readout filter and saved in the software data base.

The detector control system (DCS) is based on G64 and it was built by the team of the Wuppertal University. The crate processor is a MOTOROLA 68030. The threshold bias current is adjusted for each detector module by individual digital to analog converter (DAC).

Temperature sensors are glued onto the crown cooling tubes and on some detectors. They are read and recorded via the DCS.

The software allows us to monitor all the bias of the readout chip and the depletion voltage of the detectors. For example, during the DELPHI operation, the thresholds are automatically set low during the data taking and high during the filling of the collider and the beam tuning. Also the detector can be tuned from any laboratory by connection to the detector control workstation.

To reduce the material budget the mechanical support of the internal layer of strips and pixels are built using carbon fiber technology [7]. The detector modules are hold by one edge via thin (300 µm) ceramic supports on aluminium crowns adjusted on this carbon support. The crowns were machined to very high accuracy (5 µm) to miinimise angular dispersion of the detector modules. The modules were mounted on the crowns, then surveyed in a 3-D measuring machine (at the CPPM, Marseille) with respect to reference metal spheres. After mounting in the DELPHI vertex detector at CERN, the positions of these spheres were surveyed with respect to the global vertex detector references system.

The first layer of seventy-six modules,each of 8000 pixels, is fully mounted. One half crown (19 modules) of the second layer is presently mounted (Fig. 6), the rest is in production and will be mounted during the next LEP shutdown at the end of 1996. After installing in DELPHI, all the mounted detectors were working, except one module.

All the FASTBUS readout, cabling and DCS is installed. The monitoring software is finished and working. The histogram presenter for quality checking is being installed.

From the first on-line checks, with DELPHI closed and ready for data taking, we find, for a complete half crown (80 000 pixels) :

- threshold : 7000 e-

- number of killed noisy pixels : 161 (0.2%)

- efficiency : 99.8%

During the summer operation of DELPHI, a short appeared on two half crowns and the readout clock was missing in one other half crown, but seven half crowns were taking data during the whole periode.

12. Conclusion

The DELPHI pixel project was a challenge in many ways :

- Very tight space.

- Strong constraints on the material thickness.

- Modest budget.

- Very short time scale.

- Largest surface ever covered with pixels detectors :

We had to develop new techniques to meet these requirements :

- readout busses integrated in the detector substrate

- selective readout

Nevertheless, this year, we completed and installed in DELPHI :

- the complete first layer (76 modules of 8000 pixels)

- part of the second layer (19 modules)

The detector is starting to take data.

Fig. 1. 3-D view of the DELPHI silicon tracker

Fig. 2. Detector substrate layout

Fig. 3. Schematic drawing of the sparse data scan

Fig. 4. Efficiency versus threshold for tracks at 40°

Fig. 5. Spatial resolution versus threshold for tracks at 40°