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Different pixel detector prototypes have been produced and evaluated in the framework of the RD19 collaboration. Results from the prototypes for the WA97 (CERN-Omega) and DELPHI (CERN-LEP) experiments will be described as well as the status of the work for the implementation of such detectors in these experiments. The proposal and the prototypes for the ATLAS (CERN-LHC) experiment will also be described.

The progress in pixel detector develoment is such that we are now at the stage of proposals for large active surfaces for tracking and vertexing, using the hybrid technique. The principle is to build large size silicon detectors (8 cm long), segmented in very small pads (pixels) on which we bond electronic chips (one bump per pixel). Prototypes for an heavy ion experiment (WA97, at the SPS, CERN) and for a collider experiment (DELPHI at LEP, CERN) are already made and tested. They will be described here. The Large Hadron Collider (LHC) proposed at CERN will impose severe constraints for the detectors like high speed (25 ns crossing time), high granularity (to limit the chanel occupancy), high radiation level environment (in particular close to the beam). Pixel detectors are specially adapted to satisfy such requirements and we will describe here the proposal for the two first layers of the ATLAS inner detector.

We are building three planes of 5 x 5 cm2. Two prototypes of the electronic chip have been built [1] and the last one is fully convenient for the WA97 experiment. Each pixel includes an amplifier, a discriminator, a delay (0.5 to 2 ns), a coincidence and a latch. All this circuit is inside the detector pad surface which is 75 x 500 µm2. The bump bonding is done by solder bump of 30 x 30 µm2 using a technique developped at GEC Marconi (Caswell). Matrixes of 16 x 64 pixels have been built to be bump bonded on detector ladders of 5 cm long (see figure 1). The hole between two chips is filled by the next plane where the ladders are shifted. There are six ladders per plane.

The electronic chips have been first tested using known injected charge. The threshold fluctuations from pixel to pixel was measured by this method and found to be 75 e-r.m.s. Once the chip was bonded on a detector the noise was measured using a 109Cd source, we found 170 e- r.m.s. The test has been completed in a beam at CERN, the measured resolution was 25µm and the efficiency was better than 99.2 %.

Fig. 1 Photograph of a 5 cm ladder with 6 electronic chips bump-bonded on it (seen from the detector side).

The full detector is to be completed for the heavy ion (Pb) beam WA97.

The DELPHI collaboration wants to improve the tracking efficiency in the very forward angles by adding silicon detector layers in the forward direction [2]. From the simulations it was found that two planes of pixels followed by two planes of strips provide an efficient tracking, with less than 5% of gosts until 10 degrees from the beam (see figure 2).

Fig. 2 Ghosts calculated with different assumption (pixels = P or strips = S) for the four layers of the DELPHI VFT.

The pixel size, optimized from the tracking efficiency, the power consumption and the price is 330 x 330 µm2. The proposed layout is in the figure 3. The pixel detector module is the figure 4.

Fig. 3 Proposed layout for the DEPHI VFT

Fig. 4 DELPHI pixel detector module. 16 electronic chips are bump-bonded on a large detector wafer . The busses for the connexions between the chips and to the output cables are integrated on the detector wafer. The output cables (kapton) are bump-bonded directly on the detector wafer.

The electronic cell is similare to the one of the Omega chip, except that there is a gate after the comparator which will be open only at the beam crossing time. The readout system (sparse data scan), delivers only the address of the hit pixels [3]. The detector chip includes the busses for power, control signals and data.

For the bump bonding of the electronic chips we are studying two methods much cheaper than the one used for the omega chip. One is the screen deposit of conductive glue on the contact pad, the other is the anisotropic conductive film. Both methods are used in industry but need contact pads of 100 µm at least, which is the case of the DELPHI chip. We have already made a first test (kapton on kapton) with the anisotropic film on 300 pixels. The result is 100% of success. The resistance of the contacts is 0.170 Ohms in average.

The challenge for the DELPHI detector is that it has to be installed for the beginning of the year 1995. This means two layers in each side (backward and forward) of 48 modules of 8000 pixels each (1.2 millions of pixels on 1500 cm2).

In the letter of intent of ATLAS [4], the two first layers of the inner tracker are silicon pixel detectors. At the LHC, the working conditions are challenging:

- High level of radiations

- high resolution (which means high density of pixels and cooling problem)

- high rate of beam crossing and continuous data acquisition (fast electronics and time stamping each 25 ns).

The radiation dose at the level of the first layer (11.5 cm from the beam) is about 1014 part./cm2/year and 2.5 Mrad/year [5]. If we want to work for about 10 years we need improved technologies for the electronics. For the detector it is clear that the dammages will cause high leakage current and depletion voltage. In the case of pixels, because of the very high signal over noise, the detector thickness can be reduced by a factor of 2 with respect to the standard strip detectors,this decrease the depletion voltage by 4.

The leakage current, which is proportional to the surface of the detector element, is not important for the pixels. Therefore, because of the lower depletion voltage and the lower leakage current, one can say that the pixel detectors are more radiation hard than the strip detectors. Experiments of prototypes irradiations are under way to define the limits of radiation tolerance of the pixel detectors.

The cooling problem is a worry. If we can make pixels of 50 x 200 µm2, there will be 10000 pix/cm2 and, even if one can achiev a power consumption as small as 50 µW per pixels, that is 2.5 kW for the first layer and 3.5 kW for the second layer. We are making tests in these conditions using heat pipes and the result is a temperature gradient of less than 2°C along the detector.

The high rate of beam crossing at the LHC makes the sparse readout much more difficult than in the LEP experiments. However one can imagine several schemes and some of them are under study. One of these scheme is to use the sparse data scan as in DELPHI but with a trigger selection before. The easyest way to make a trigger selection is an "AND" between the trigger and the delayed signals but this needs a precise delay (st<5ns) in each pixel. The proposition is to put the "AND" at the end of each line and each column. Other readout schemes proceeds by column like the BCO number storage (BL/USA) or data compacting before trigger selection (CPPM, Marseille).

The technology of the pixel detectors is now at the stage were we can propose large tracking layers. The electronics can be optimized for each type of experiment. In the inner detector of ATLAS, the improvement in tracking efficiency ant ghost rejection is completed by a better radiation hardness.

[1] H.Beker et al. A hybrid silicon pixel telescope tested in a heavy ion experiment. NIM A332(1993)188.

[2] Proposal for a very forward tracker for DELPHI CERN/LEPC/93-6

[3] P.Delpierre, JJ.Jaeger NIM A305(1991)627

JJ.Jaeger et al. A sparse data scan circuit for pixel detector readout. Proceedings of the IEEE Nuclear sciences symposium, Orlando, 1992.

[4] ATLAS Letter of intent, CERN/LHCC/92.

[5] T. Mouthy, Radiation dose expected in the LHC Inner Detector : update. 6 Oct.93, ATLAS-INDET-28.

Fig. 1 Photograph of a 5 cm ladder with 6 electronic chips bump-bonded on it (seen from the detector side).

Fig. 2 Ghosts calculated with different assumption (pixels = P or strips = S) for the four layers of the DELPHI VFT.

Fig. 3 Proposed layout for the DEPHI VFT

Fig. 4 DELPHI pixel detector module. 16 electronic chips are bump-bonded on a large detector wafer . The busses for the connexions between the chips and to the output cables are integrated on the detector wafer. The output cables (kapton) are bump-bonded directly on the detector wafer.